With more and more clocks having different phases being used in today's chips, there is often the need to switch the source clock to be used while the chip is running. Usually, the switching the source clock between two clocks having different phases is done by using a multiplexer in the hardware and may have a switch signal line to trigger the switching motion. The control signal is sometimes called “select” as we shall see in later references. Please refer to FIG. 1, which shows a traditional delay clock switching scheme. The upper area of FIG. 1 is the circuitry of the traditional delay clock switching and the lower area is the timing scheme of the clocks including clock_A, clock_B, clock_C, the “select” (switch signal), and the output clock. In this embodiment, the source clock signal is inputted from the “IN” side, through an operation device named A, through a second device named B, then through one other device named C. Three lines are stretched out from three points A, B, C to be connected to the delay selector which receives all three clocks, clock_A, clock_B and clock_C having phase difference from each other as shown in the timing scheme. The delay selector generates an output clock on the output clock line (it's shown as “OUT” in FIG. 1). At the time point_A, the delay selector receives a control signal aforementioned “select”, which is switching from B to C shown in FIG. 1. The timing scheme means that the delay selector switches the output clock from clock_B to clock_C at the time point_A by the select from B to C. As a result, a glitch happens due to the immediate switching of the output clock from clock_B to clock_C when the select value changes.
Furthermore, please refer to FIG. 2, a delay clock switching scheme of another embodiment that the clock switching progresses in a conventional way. As the same of FIG. 1, the upper area of FIG. 2 is the circuitry of the traditional delay clock switching and the lower area of FIG. 2 is the timing scheme of the clocks including clock_A, clock_B, a switch signal (select), and an output clock. In this embodiment, the source clock signal is inputted from the “IN” side, then to be split into two clocks having phase difference, clock_A and clock_B. Two lines are stretched out to connect a multiplexer as an output device to generate the output clock. In this case, at the time point_A, the clock_A is progressing at the rising edge of the phase; and at the time point_B, the clock_B is progressing at the rising edge of the phase. However, the select changes at the time point in-between. The outcome of the glitch happening cannot be avoided due to the immediate switching of the output clock from clock_A to clock_B when the select value changes.
In the prior art, either of the embodiment shown in FIG. 1 or in FIG. 2, cannot prevent the glitch from happening at the output clock because of the circuitry design to provide only the immediate switching of the output clock. However, with more and more clocks having different phases necessary to be used in today's chips, the prevention of glitch happening at the switching clock at any time point reference becomes an important topic. This importance is especially apparent when the chip today is getting more complicated and multi-functional, even more source clocks are to be implemented and switched as a reference for perhaps thousands of processes in chip thereafter. A precise and clear clock without any glitch is necessary for a chip to keep a smooth operation inside or even to avoid the whole chip operation of a crash down. Consequently, there is a need to develop a system and method for clock-switching to provide prevention against glitches at the output clock.